This disclosure relates generally to the field of computer hardware design, and more specifically to a floorplan of a floating point unit.
A floating point unit (FPU) is a part of a computer system designed to carry out operations on floating point numbers. Operations may include addition, subtraction, multiplication, fused multiplication and addition, fused multiplication and subtraction, division, square root, and/or exponential or trigonometric calculations. A FPU may comprise a plurality of functional blocks, including but not limited to a frontend, an aligner, a multiplier, an adder, a normalizer, and a rounder. The speed of the FPU may significantly affect the speed of the computer system as a whole, and the speed of the FPU is determined in part by the physical layout, or floorplan, of the functional blocks.
Optimizing a high-frequency FPU floorplan for speed and size presents various challenges, such as minimizing wire delay between functional blocks (i.e., minimizing the length of time it takes for a signal to propagate from one block to another) and avoiding wire congestion. Functional blocks may be connected by default wires or by good wires. The width of a default wire is the minimum wire width suitable for technology. A good wire has a width which is an integer multiple of the width of a default wire. Signals may take a whole cycle to propagate from one corner of the FPU to the opposite corner on a default wire; a good wire provides a significantly faster connection. However, a default wire is smaller and consumes less power than a good wire. Paths between the major functional blocks of the FPU may require good wires to maximize speed of operation of the FPU, but the number and length of good wires that may be used in the FPU floorplan is limited, due to wire congestion and space constraints. Also, longer wires of either type may require buffering, while shorter wires may not; therefore, shorter wires are desirable when possible.
There is therefore a need for an optimized floorplan for a FPU, and a method of making an FPU with an optimized floorplan.